Much of two months wasted through compiler changes - Quartus v13.0 sp1.

Back in 2008 I designed and built a Cyclone I based USB interfaced instrument, which has been working flawlessly in my academic research lab 24/7.

However that FPGA module is no longer available, and Cyclone I is no longer supported in the current Web based Quartus II offering, so I decided to build an upgraded USB2 interfaced version, based on an FTDI Morphic II module, which uses the Cyclone II.

I laid out a PCB, and in early August stitched together my well-tested USB2 interface software with the original instrument block diagram, etc, and, I am afraid, expected it to all work.

Now I can not work on such things full time, I have to keep the lab running, but some weeks in August were lost because, at the top level, the Quartus 13.0 sp1 compiler was randomly changing already correctly assigned I/O pins. This first problem and its resolution is discussed in thread :

http://www.alteraforum.com/forum/showthread.php?t=41852

Fortunately this does not seem to have damaged any of the chips.

The second problem has taken me much of September to track, requiring much testing with a scope, to identify what was going wrong, and then the installation of ModelSim (and learning to drive it) to localise the problem. This is partly because the problem was occurring in a well tested low-level, unchanged, block-diagram, not in code that was new or changed.

The scope testing showed that what was supposed to be a USB configurable set of 8/16/24/32 bit data transfer bursts, was not happing correctly. Tracing the information through the system, it was clear that the corruption was not happening in any of the upper level or recently written code, but in the low-level un-changed block diagram. My first assumption was that there was a timing error in the counters due to the different host FPGA, but simulation showed that the control information used to configure 8/16/24/32 bit data transfer bursts was not actually reaching the relevant counter, so as to be loaded into it :

https://www.alteraforum.com/forum/attachment.php?attachmentid=7781

I seems that version v13.0 sp1 of the Quartus II compiler is no longer joining bus nodes together, just by naming them - no compiler errors, just does not join them, as shown by the above ModelSim simulation. I had to insert a new component "wire", between the nodes, to join them :

https://www.alteraforum.com/forum/attachment.php?attachmentid=7782

This now works fine, as designed, as in the 2008 version; here are 16/24/32 bit data transfer bursts now working correctly :

https://www.alteraforum.com/forum/attachment.php?attachmentid=7783

The instrument is now cased and working fine, but that time could certainly have been better used on the research.