mSGDMA: Incorrect operation but the behavior changes when SignalTapII is inserted.

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8. The mm-master of msgdma_ur1 and msgdma_uw1 is of a 512-bit width @ 150mhz.

They each have configurations of

burst length is 0x20

command FIFO depth 128

descriptor FIFO depth 128

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When I disabled the burst transfer, then the mSGDMAs work completely.

However, the DDR3 memory throughput gets very low. I need burst transfer.

For max burst count = 2, 8, and 64, the mSGDMA modules have the same failure as that for max burst count = 32.

Mickycat