Occasional ContributorMPFE for Stratix 10 EMIF?
Hello,
For past designs, I've used the UniPHY SDRAM memory controller for a DDR memory interface. That controller contained a multi-port front end (MPFE) which could be used to create multiple smaller ports for accessing the DDR memory from user logic.
I'm now working on a Stratix 10 design using the EMIF interface, and there does not seem to be a similar MPFE feature available. The only avalon port provided to user logic has a 256-bit data port.
Is there some other Platform Designer component available to split a 256-bit avalon bus into separate smaller buses? Or is that something I will need to do in user logic?
Thanks,
Terry
OK, thanks. I don't think SGDMA is going to work for our application, since we have multiple masters who need to access the memory.
Intel should consider bringing back the MPFE for the newer EMIF IP core. That was a really useful feature. To get rid of that without an equivalent replacement makes porting older designs to newer device architectures extra difficult.
--
Terry
