Forum Discussion
Occasional ContributorMPFE for Stratix 10 EMIF?
Hello,
For past designs, I've used the UniPHY SDRAM memory controller for a DDR memory interface. That controller contained a multi-port front end (MPFE) which could be used to create multiple smaller ports for accessing the DDR memory from user logic.
I'm now working on a Stratix 10 design using the EMIF interface, and there does not seem to be a similar MPFE feature available. The only avalon port provided to user logic has a 256-bit data port.
Is there some other Platform Designer component available to split a 256-bit avalon bus into separate smaller buses? Or is that something I will need to do in user logic?
Thanks,
Terry
OK, thanks. I don't think SGDMA is going to work for our application, since we have multiple masters who need to access the memory.
Intel should consider bringing back the MPFE for the newer EMIF IP core. That was a really useful feature. To get rid of that without an equivalent replacement makes porting older designs to newer device architectures extra difficult.
--
Terry
8 Replies
AdzimZM_AlteraRegular Contributor
Hi Terry,
There is a component in the Platform Designer that you can work with.
It's Avalon Streaming Splitter Intel FPGA IP.
I think you can visit to this link for a reference resource.
https://www.intel.com/content/www/us/en/docs/programmable/683130/21-4/st-splitter-core.html
Thanks,
Adzim
GLT1Hi Adzim,
That might work, but the port out of the EMIF core is Avalon-MM rather than Avalon-ST.
Are there components to convert MM to ST and then from ST back to MM? I can't seem to find anything like that in the Platform Designer IP list.
Thank you,
Terry
- AdzimZM_Altera
Hi Terry,
The Quartus doesn't has a direct convertor from the Avalon MM to Avalon ST and vise versa.
My suggestion is you can use SGDMA core.
You also can refer to this forum link for another option.
Sometimes the users will create their own custom convertor because the component is not match with their configuration.
Regards,
Adzim
- GLT1
OK, thanks. I don't think SGDMA is going to work for our application, since we have multiple masters who need to access the memory.
Intel should consider bringing back the MPFE for the newer EMIF IP core. That was a really useful feature. To get rid of that without an equivalent replacement makes porting older designs to newer device architectures extra difficult.
--
Terry
- AdzimZM_Altera
Hi Terry,
Maybe you can use Arbitration module for your configuration.
https://www.intel.com/content/www/us/en/docs/programmable/683364/18-1/arbitration.html
Regards,
Adzim
- AdzimZM_Altera
Hi Terry,
Do you have any further question regarding to this topic?
Regards,
Adzim
- AdzimZM_Altera
We do not receive any response from you to the previous reply that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
- GLT1
Adzim,
I will look into using the arbitration modules to help with our design. I don't have any other questions on this, so you can close the thread.
Thank you,
Terry
