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Altera_Forum's avatar
Altera_Forum
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9 years ago

Module output gives high impedence when connected to the inout port of another module

I have created a module which calls another module within it's body, and the final output of the output module gives me the desired output. But when I connect this output wire to the 'inout' port of another module(bidir_switch) ,the output of the former module(Outer) as well as inout port goes to high impedance. Please find the basic structure of the actual code below(sorry, the actual code is too big). Could you please provide some insight into this problem? I have been trying to debug this problem for almost a week now :-/

module testbench();

reg in1,in2,clk;

wire out,d1;

Outer O(.in1(in1),.in2(in2),.out.(out),.clk(clk));

bidir_switch BS(.a1(d1),.a2(out),.control(1'b1));

endmodule

module bidir_switch(a1,a2,control);

inout a1,a2;

input control;

tranif1(a1,a2,control);

endmodule

module Outer(in1,in2,out,clk);

input in1,in2,clk;

output out;

inner1 I1(i1.(in1),i2.(in2),o.(out),.clk(clk));

endmodule

module inner1(i1,i2,o,clk);

input i1,i2,clk;

output o;

inner2 I2(q1.(out1),q2.(in3),qo.(o),.clk(clk));

endmodule

inner2(q1,q2,qo,clk);

input q1,q2,clk;

output reg qo;

always@(posedge clk)

begin

qo <= q1;

end

endmodule

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    Hello Krish_pathi,

    From what I read you could be bumping into a similar problem I had some time ago reading from a GPIO port :

    FPGA's are a bit different from Computer programming.

    You do not 'CALL' a routine, you instantiate a hardware object.

    Therefore: if you connect 2 ports, 1 output and 1 inout port, you have to 'tell' the inout port that it needs to go into the state of high impedance in order to enable the port on the other side, to drive the line connecting the 2 ports. If both sides would want to drive the connecting line and 1 port wants high and other side low you end up with a short circuit.

    In practice: you assign 'z' of high impedance to the inout port you need to to read from.

    module tri_buf (a,b,enable);

    2 input a;

    3 output b;

    4 input enable;

    5 wire a,enable;

    6 wire b;

    7

    8 assign b = (enable) ? a : 1'bz;

    9

    10 endmodule

    I hope this can help,

    Best regards,

    Johi