Module output gives high impedence when connected to the inout port of another module

Hello Krish_pathi,

From what I read you could be bumping into a similar problem I had some time ago reading from a GPIO port :

FPGA's are a bit different from Computer programming.

You do not 'CALL' a routine, you instantiate a hardware object.

Therefore: if you connect 2 ports, 1 output and 1 inout port, you have to 'tell' the inout port that it needs to go into the state of high impedance in order to enable the port on the other side, to drive the line connecting the 2 ports. If both sides would want to drive the connecting line and 1 port wants high and other side low you end up with a short circuit.

In practice: you assign 'z' of high impedance to the inout port you need to to read from.

module tri_buf (a,b,enable);

2 input a;

3 output b;

4 input enable;

5 wire a,enable;

6 wire b;

7

8 assign b = (enable) ? a : 1'bz;

9

10 endmodule

I hope this can help,

Best regards,

Johi