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chipper's avatar
chipper
Icon for New Contributor rankNew Contributor
2 years ago

Module logic use report as 0

Hi, New to Quartus Prime. I created several modules, but their reported logic use is 0, even though the modules are included in the RTL viewer and connect to IO. Is that normal, or does it mean som...
Hdl
FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
2 years ago

Hi,

there's something wrong, the modules have apparently no actual function in your design.

General rule: design logic will be discarded in synthesis if no output depends on it. Possible reasons: no output signals connected, missing clock, module stuck in reset.