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Altera_Forum
Honored Contributor
Honored ContributorModule Declaration Question for Transceiver Design
Hi, I was hoping someone could answer a fairly simple question. Here is my module declaration code for a transceiver design: module xcvr_prbs ( //inputs input wire phy_mgmt_clk, input ...
Altera_ForumHonored Contributor
Honored ContributorThere are two styles of module header declarations; one from Verilog-1995 where you might have to mention a port name up to three times, and the one you are using from Verilog-2001 and later where everything is in one place.
See http://stackoverflow.com/questions/12229477/why-are-output-nets-also-required-to-be-redeclared-as-either-wire-or-reg
