module cannot be declared more than once

After generating the .qsys file when I am trying to run the top module verilog file in quartus II it is giving error :Error (10228): Verilog HDL error at gmmpipe.v(6): module "gmmpipe" cannot be declared more than once. I gave gmm_accelerator.v and gmmpipe.v module during qsys generation .In includes the gmmpipe.v module. I am attaching both the module. How to fix this error? Please help.