Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

module cannot be declared more than once

After generating the .qsys file when I am trying to run the top module verilog file in quartus II it is giving error :Error (10228): Verilog HDL error at gmmpipe.v(6): module "gmmpipe" cannot be decl...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Hi Bhaumik,

No, I didn't add the original file in my project in quartus II. I added only qsys_system.qip file in my project.