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Altera_Forum's avatar
Altera_Forum
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11 years ago

module cannot be declared more than once

After generating the .qsys file when I am trying to run the top module verilog file in quartus II it is giving error :Error (10228): Verilog HDL error at gmmpipe.v(6): module "gmmpipe" cannot be decl...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Hi,

Whenever you generate QSYS system, all verilog source files are copied into folder/submodules where folder will have same name as of your QSYS system in your project. So there will be one copy of your file in that submodules folder.

If you have your original file also added in your project, then you may see this error.

One thing you can do is Double click on that error and see to which file it points. In this way, you may be able to find it out.

Hope this helps.

Cheers,

Bhaumik