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Altera_Forum's avatar
Altera_Forum
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15 years ago

modelsim: (vsim-3053) Illegal output or inout port connection

Hi guys,

I have an output port (reg) in a module. That module is instantiated in my top level module, with that output signal as wire to a pin on the CPLD.

I don't assign anything to this in my tb (since it would be an input into the tb).

But I still get the above error from Modelsim. The compilation goes through fine which makes me think that my tb has an issue. But I do nothing with this signal in my tb.

Any thoughts?:(

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    so in your top level design file your signal is defined as a wire. You then instansiate this in to your tb but don't assign it. so you instansiation will be .mysignal (), This should work so it must be a syntax error.

    do you have `default_nettype none set at the top of your module. This forces you to declare all your signals so you don't make mistakes.