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- Altera_Forum
Honored Contributor
"global" is a SystemVerilog keyword.
I cannot compile one of my verilog files in modelsim altera edition. I get this error using the global primitive.
# ** Error: (390): near "b2v_inst1": syntax error, unexpected IDENTIFIER, expecting clocking global b2v_inst1( .in(LCLK1), .out(g_lclk1_c0)); Any ideas on how to fix ? Thanks."global" is a SystemVerilog keyword.