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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

ModelSim "True Dual Port" Memory viewer weird

Hi everyone. I have a question for you all. I have a FPGA VHDL design using Cyclone III, in my design I used internal memory configured as true dual port RAM. I created the VHDL code, simu...
DogZapper's avatar
DogZapper
Icon for New Contributor rankNew Contributor
1 year ago

So, I got this same issue. According to what I read above, I'm just suppose to ignore the data contents of all "U"s in memory B. Then why does modelSim even produce a memory_B? I have some code that is not working and I'm trying to fix it. I thought maybe I had a memory issue, but maybe not? I don't understand modelSim's depiction of memory using A&B outputs?