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Altera_Forum's avatar
Altera_Forum
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15 years ago

ModelSim "True Dual Port" Memory viewer weird

Hi everyone. I have a question for you all. I have a FPGA VHDL design using Cyclone III, in my design I used internal memory configured as true dual port RAM. I created the VHDL code, simu...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I wouldnt be surprised if it only used the port A storage - it is stored in a variable inside a process in the code. On the real hardware there is only 1 memory area for the two ports anyway. If "m_mem_data_b" is always 'U', it just means it is never assigned anything - if your design is working then Im presuming it only ever puts data into "m_mem_data_a". This models realistic behaviour.

if it works, dont worry.