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Altera_Forum
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15 years ago

ModelSim "True Dual Port" Memory viewer weird

Hi everyone. I have a question for you all. I have a FPGA VHDL design using Cyclone III, in my design I used internal memory configured as true dual port RAM. I created the VHDL code, simu...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

No, I write data into Port B, after writing sequence finished then I read data inside memory from Port A. So I don't read data being written in the same time.

Darkwave, do you have any idea?

thanks,...