ModelSim SystemVerilog compile error

Folks,

I am unable to make sense of an error I get while using ModelSim.

My SystemVerilog module is:

///////////////////BEGIN MODULE/////////////////////////////

module op_transform(input logic[31:0] data, output y);

typedef struct packed {

logic[11:0] op1;

logic[11:0] op2;

} op_str;

op_str my_op_str = 24'hBE_EE_FE;

always_comb begin

if (data > 1024)

opTF(data, my_op_str.op1, my_op_str.op2);

end

task automatic opTF(input logic[31:0] data, ref logic[11:0] opA, ref logic[11:0] op ) ;

/* Code omitted for brevity */

endtask

endmodule

///////////////////END MODULE/////////////////////////////

Quartus Analysis & Synthesis completes without errors.

But when I attempt to compile this in ModelSim, I get the following errors:# ** Error: <filename>.sv(12): The select "my_op_str.op1" into a packed value is illegal for use with ref argument "opA".# ** Error: <filename>.sv(12): The select "my_op_str.op2" into a packed value is illegal for use with ref argument "opB".

Has anybody seen this before?

If I individually list the members of the struct in the module, ModelSim compiles fine. What am I missing?

Any help would be appreciated. Thanks in advance!