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Altera_Forum's avatar
Altera_Forum
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14 years ago

ModelSim SystemVerilog compile error

Folks, I am unable to make sense of an error I get while using ModelSim. My SystemVerilog module is: ///////////////////BEGIN MODULE///////////////////////////// module op_transform...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Thanks, that's what I figured. An inout did just fine, although there is a copy before and after making the call.

Your suggestion to make opTF a function is good.

Its strange that Quartus does not complain during Analysis & Synthesis but ModelSim does during compilation.

Thanks!