Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorModelsim Simulation VHO vs VHDL files
I realized there is difference in output obtained from Altera-Modelsim simulation using .vho file (full compilation file from Quartus) and using the vhdl files directly. Any explanations for this ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- What you have posted is fairly meaningless without the code. But you say they design was asynchronous, but every component uses a clock - is it not synchronous? --- Quote End --- Sorry I got mixed up with my another coding. Yea this one is synchronous system and the output are same for both VHO simulation and filesimulation but difference in the arrival of the outdata. VHO simulation produces an additional clock cycle compare to filesimulation.