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Altera_Forum
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9 years ago

Modelsim Simulation VHO vs VHDL files

I realized there is difference in output obtained from Altera-Modelsim simulation using .vho file (full compilation file from Quartus) and using the vhdl files directly. Any explanations for this ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

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The simulation from the compiled VHO files will reflect what is likely to happen on the chip. If it is asynchronous then I suspect you didnt take into account logic path delays in your design.

Asynchronous designs are tricky to work with as they are full of race conditions and timing issues, and can be affected by PVT (process, voltage, temperature). I highly suggest you synchronise your design (what FPGAs are designed for) as it makes a design predictable.

It might be worth posting your code to see if we can see any problems with it.

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I will try to look into the codings again. The code is quite messy at the moment, however I have posted the top levels and also the simulation waveform using both VHO file and VHDL files.

Hopefully someone can pinpoint my mistakes here.

Thanks alot