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Altera_Forum
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12 years ago

ModelSim simulation result is different to run in real FPGA

We use an EP1C6T144 chip as an SPI master to receive data from ADCs. The FPGA state machine is successful and receives data correctly in ModelSim simulation, but always shorts 1 bit shift if run on r...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

You forget one important thing - synthesis ignores sensitivity lists. So if you miss signals out you only cause the simulation to be wrong compared to the hardware.