Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Modelsim simulation problem: altfp_mult floating point multiplier Megafunction

Hallo everybody,

i have a problem when doing a functional simulation on Altera altfp_mult Megafunction:

I configured the Megafunction to multiply two 32 bit floats with 5 clock cycles latency, and Modelsim shows me an unknown state of bits 30-23 after 2 clock cycles. However, the result after 5 clock cycles is correct. This behavior only occures with the first multiplication, if a change inputs after 5 clock cylces, i will get the right result without this strange behavior.

The big problem ist that i want to cascade more multipliers and floating point adders for a PID controller, and if the first multiplication is wrong, the whole simulation will fail.

I have implemented the multiplier on my Cyclon III Starter Kit and checkt the multiplier with Signal Tap. In rela life i could not monitor any strange behavior, so a guess that it is a simulation error, or that something is wrong with my simulation settings.

Please see the attached picture of the simulation. I created the Megafunction with the Quartus II MegaWizard. My Modelsim projects include only the altfp_mult vhdl file and one testbench file to generate the clock an the stimuli. I will post this files and project settings if necessary.

data_in_a and data_in_b are the inputs of the multiplier, res is the output.

Signal clk is the clock signal. I hard-wired clk_en to '1' and aclr to '0'. Signals nan, ov, uv and zero a the flags of the multiplier.

Can anybody tell me why this thing happens, and how can i avoid this behavior?

Thanks in advance,

magixD

12 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    anyone can tell me how to use altf_mult megawizard with pio via nios correctly please , send me the code c if it is possible and thank you very match

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    Thanks for you replies!

    @FvM:

    My problem is that i want the output to be 0X00000000 until the vlaid result is avaiable. I have cascaded many multipliers an adders, so anything other than '0' or '1' will mess up the whole simulation.

    --- Quote End ---

    This will not be a problem. Inputs into other FPmults with 'X's will just cause output 'X's, but for 2 chained multipliers the result latency will be 10 clocks, and all output after 10 clocks will be valid, no matter what the indetermined state was. If this messes up the testbench, I think you may have designed the TB wrong.

    Why not have a 1 bit "valid" flag that runs parrallel to the data? you will need this (or a clock enable) if you have a bursty input anyway.