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Thanks for you replies!
@FvM:
My problem is that i want the output to be 0X00000000 until the vlaid result is avaiable. I have cascaded many multipliers an adders, so anything other than '0' or '1' will mess up the whole simulation.
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This will not be a problem. Inputs into other FPmults with 'X's will just cause output 'X's, but for 2 chained multipliers the result latency will be 10 clocks, and all output after 10 clocks will be valid, no matter what the indetermined state was. If this messes up the testbench, I think you may have designed the TB wrong.
Why not have a 1 bit "valid" flag that runs parrallel to the data? you will need this (or a clock enable) if you have a bursty input anyway.
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