ModelSim RTL simulation works, now gate-level simulation

My design is in Quartus II and I can simulate it at the RTL succesfully. I compiled the design and want to simulate it at the gate-level. There are many signals missing and new signals whose purpose I don't know -- probably due to the compiler. More importantly, I can't see any signals in any of the instantiated modules -- I can only see the signals in the top level (the ones not synthesized away).

In the ModelSim "Start Simulation" dialog window, I notice that "rtl_work" contains the three Verilog source files, but "gate_work" contains only the file I designated as top-level.