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Altera_Forum
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16 years ago

ModelSim: no ouput for assert statement

Hallo, I started to experiment with VHDL simulation and verification lately, so I wrote a testbench and simulated it with ModelSim-Altera 6.e1 Starter Edition. The testbench includes some asser...
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Altera_Forum
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16 years ago

The report part of an assert only occurs if the statement is false. The way I remember it is:

assert (all is good) report "all is not good" severity failure;