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Altera_Forum's avatar
Altera_Forum
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16 years ago

ModelSim: no ouput for assert statement

Hallo,

I started to experiment with VHDL simulation and verification lately, so I wrote a testbench and simulated it with ModelSim-Altera 6.e1 Starter Edition. The testbench includes some assert statments but unfortunatly Modelsim doesn't display any errors when this assert statements are executed. I enabled "Enable assertion debug" in the Simulation Properties window and checked the settings in the Runtime Options window.

Can anybody tell me how i get Modelsim to display an error-message when an assert statement is executed?

The testbench can be downloaded here (http://www.stefanvhdl.com/vhdl/vhdl/tb1.vhd) (it's from an online course (http://%3cbr%20/%3e%0ahttp://www.stefanvhdl.com/vhdl/html/basic_stim_gen.html))

Thanks in advance,

magixD

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    The report part of an assert only occurs if the statement is false. The way I remember it is:

    assert (all is good) report "all is not good" severity failure;
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Hi,

    I know, I wrote the assert statement so that 'all is not good' ;)

    This is the source code again (it's the same as in the link from the first post): 

    library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.std_logic_arith.all;
use work.txt_util.all;
entity TB1 is
end TB1; 
architecture test of TB1 is
    signal x1:    std_logic;
    signal x2:    std_logic;
    signal y:     std_logic;
begin
test_seq: process
    variable cnt: integer := 0;
    --*variable slv: std_logic_vector(X2'range);
begin
    x1 <= '0';
    x2 <= '0';
    wait for 10 ns;
    x1 <= '1';
    x2 <= '0';
    wait for 10 ns;
         
    x1 <= '0';
    x2 <= '1';
    wait for 10 ns;
    x1 <= '1';
    x2 <= '1';      
    wait for 10 ns;
    assert y = (x1 xor x2)
      report "E@TB: circuit failed"
      severity Error;
    assert y = (x1 xor x2)
        report "E@TB: failure at: x1="& std_logic'image(x1)&
                " x2="& std_logic'image(x2)
        severity Error;
      
    assert y = (x1 xor x2)
        report "E@TB: failure at: x1="& str(x1)& " x2="& str(x2)
        severity Error;
    x1 <= 'X';
    x2 <= 'X';
    wait for 30 ns;
    x1 <= '1', '0' after 10 ns, '1' after 20 ns, '0' after 30 ns;
    x2 <= '1', '0' after 20 ns;
    wait; -- stop process
end process test_seq;
    -- this is supposed to be an xor ... but it isn't
    y <= (x1 and not x2) or (x2 and not x1) or (x1 and x2);
end test;