Honored Contributor
Honored ContributorA usual reason for 'Z' logic values is that design entitities haven't been loaded during simulation startup. You allways get a warning then, but it may be overlooked among a shower of informational messages. ModelSim can simulate Altera Megafunctions and device specific hardware very good, but the libraries, e. g. altera_mf must be present. I'm not familiar to the ModelSim Altera Edition or Verilog simulation, so I just can say: follow the suggestions in the documentation and check the warnings during simulation.
Another possible source of 'Z' states is using a PLL without the necessary 1 ps timing resolution. All PLL generated clocks remain inactive then.
