Altera_Forum
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12 years ago[ModelSim] Maximum of 32bit vector wave is supported
I am trying to simulate a vhdl design i've made which takes in a 48bit key as an input however when I try and simulate this with modelsim-altera I am getting an error saying that maximum of 32bit vector wave is supported. How can I get around this problem? Is it because the free versions only support 32bit input vectors?
The line of code in my VHDL entity looks like:K : IN STD_LOGIC_VECTOR(47 DOWNTO 0); And the exact error looks like: Maximum of 32bit vector wave is supported