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Altera_Forum
Honored Contributor
9 years agoHi,
attached the two files from "C:\intelFPGA_lite\16.1\modelsim_ase\examples\tutorials\verilog\basicSimulation"Hi,
attached the two files from "C:\intelFPGA_lite\16.1\modelsim_ase\examples\tutorials\verilog\basicSimulation"