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FMors's avatar
FMors
Icon for New Contributor rankNew Contributor
7 years ago

Modelsim, Instantiation of 'dffeas' failed. The design unit was not found.

Hi,

I have an error using

Quartus Prime 18.1.0 Build 625 9/12/2018 SJ Lite version

and

ModelSim - INTEL FPGA STARTER EDITION 10.5b Revision: 2016.10 Date: Oct 5 2016.

Device: Cyclone10 (10CL016YU256C8G) as on Arduino VIDOR4000 board.

Circuit: a simple 7-bit counter.

Log transcript on Modelsim:

# vsim -gui -l msim_transcript -L cyclone10lp_ver -L work testbench

# Start time: 09:38:29 on Jan 09,2019

# Loading work.testbench

# Loading work.prove_project

# Loading cyclone10lp_ver.cyclone10lp_io_obuf

# Loading cyclone10lp_ver.cyclone10lp_io_ibuf

# Loading cyclone10lp_ver.cyclone10lp_clkctrl

# Loading cyclone10lp_ver.cyclone10lp_mux41

# Loading cyclone10lp_ver.cyclone10lp_ena_reg

# Loading cyclone10lp_ver.cyclone10lp_lcell_comb

# ** Error: (vsim-3033) prove_project.vo(2025): Instantiation of 'dffeas' failed. The design unit was not found.

# Time: 0 ps Iteration: 0 Instance: /testbench/pproj File: prove_project.vo

# Searched libraries:

# C:/intelFPGA/18.1/modelsim_ase/altera/verilog/cyclone10lp

# D:/PROGETTI/ARDUINO/Vidor4000/VidorBitstream-release/projects/MKRVIDOR4000_prova/projects/MKRVIDOR4000_prova/simulation/modelsim/gate_work

# ** Error: (vsim-3033) prove_project.vo(2062): Instantiation of 'dffeas' failed. The design unit was not found.

# Time: 0 ps Iteration: 0 Instance: /testbench/pproj File: prove_project.vo

# Searched libraries:

# C:/intelFPGA/18.1/modelsim_ase/altera/verilog/cyclone10lp

# D:/PROGETTI/ARDUINO/Vidor4000/VidorBitstream-release/projects/MKRVIDOR4000_prova/projects/MKRVIDOR4000_prova/simulation/modelsim/gate_work

# ** Error: (vsim-3033) prove_project.vo(2099): Instantiation of 'dffeas' failed. The design unit was not found.

# Time: 0 ps Iteration: 0 Instance: /testbench/pproj File: prove_project.vo

# Searched libraries:

# C:/intelFPGA/18.1/modelsim_ase/altera/verilog/cyclone10lp

# D:/PROGETTI/ARDUINO/Vidor4000/VidorBitstream-release/projects/MKRVIDOR4000_prova/projects/MKRVIDOR4000_prova/simulation/modelsim/gate_work

# ** Error: (vsim-3033) prove_project.vo(2136): Instantiation of 'dffeas' failed. The design unit was not found.

# Time: 0 ps Iteration: 0 Instance: /testbench/pproj File: prove_project.vo

# Searched libraries:

# C:/intelFPGA/18.1/modelsim_ase/altera/verilog/cyclone10lp

# D:/PROGETTI/ARDUINO/Vidor4000/VidorBitstream-release/projects/MKRVIDOR4000_prova/projects/MKRVIDOR4000_prova/simulation/modelsim/gate_work

# ** Error: (vsim-3033) prove_project.vo(2173): Instantiation of 'dffeas' failed. The design unit was not found.

# Time: 0 ps Iteration: 0 Instance: /testbench/pproj File: prove_project.vo

# Searched libraries:

# C:/intelFPGA/18.1/modelsim_ase/altera/verilog/cyclone10lp

# D:/PROGETTI/ARDUINO/Vidor4000/VidorBitstream-release/projects/MKRVIDOR4000_prova/projects/MKRVIDOR4000_prova/simulation/modelsim/gate_work

# ** Error: (vsim-3033) prove_project.vo(2210): Instantiation of 'dffeas' failed. The design unit was not found.

# Time: 0 ps Iteration: 0 Instance: /testbench/pproj File: prove_project.vo

# Searched libraries:

# C:/intelFPGA/18.1/modelsim_ase/altera/verilog/cyclone10lp

# D:/PROGETTI/ARDUINO/Vidor4000/VidorBitstream-release/projects/MKRVIDOR4000_prova/projects/MKRVIDOR4000_prova/simulation/modelsim/gate_work

# ** Error: (vsim-3033) prove_project.vo(2246): Instantiation of 'dffeas' failed. The design unit was not found.

# Time: 0 ps Iteration: 0 Instance: /testbench/pproj File: prove_project.vo

# Searched libraries:

# C:/intelFPGA/18.1/modelsim_ase/altera/verilog/cyclone10lp

# D:/PROGETTI/ARDUINO/Vidor4000/VidorBitstream-release/projects/MKRVIDOR4000_prova/projects/MKRVIDOR4000_prova/simulation/modelsim/gate_work

# Error loading design

# Error: Error loading design

---------------

Thanks for the help.

Fabio

4 Replies

  • Abe's avatar
    Abe
    Icon for Frequent Contributor rankFrequent Contributor
    7 years ago

    You have to include the following libraries while simulating..

    vsim -gui -l msim_transcript -L cyclone10lp_ver -L altera_ver -L altera_lnsim_ver -L 220model_ver -L altera_mf_ver -L work testbench

    This will include the required libraries for the simulation.

  • FMors's avatar
    FMors
    Icon for New Contributor rankNew Contributor
    7 years ago

    Anand, the fastest way is to include the dffeas.v file in the compilation command line of my testbench.v

    vlog -work work testbench_VIDOR4000/testbench.v C:/intelFPGA_lite/18.1/quartus/eda/fv_lib/verilog/dffeas.v

    But, I should do that for all future "not found" modules, so the way proposed by Abe (provided the additional libraries

    contain all existing modules) seems to me better and it works.

    Thanks both!

    Fabio

  • AnandRaj_S_Intel's avatar
    AnandRaj_S_Intel
    Icon for Regular Contributor rankRegular Contributor
    7 years ago

    Hi,

    Try to compile the dffeas library.

    You can find the file in directory C:\intelFPGA_lite\18.1\quartus\eda\fv_lib\verilog\dffeas.v

    Steps

    1. vlib cyclone10lp_ver
    2. vmap cyclone10lp_ver cyclone10lp_ver
    3. vlog -work cyclone10lp_ver C:/intelFPGA_lite/18.1/quartus/eda/fv_lib/verilog/dffeas.v

    Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

    Regards

    Anand

  • FMors's avatar
    FMors
    Icon for New Contributor rankNew Contributor
    7 years ago

    Another thing maybe related: when I do simulation break in the log window appears the erro message below.

    run -all

    # Break key hit

    # Break in Module cyclone10lp_lcell_comb at /build/swbuild/SJ/nightly/18.1std/625/l64/work/modelsim/eda/sim_lib/cyclone10lp_atoms.v line 4250

    # Error opening D:/build/swbuild/SJ/nightly/18.1std/625/l64/work/modelsim/eda/sim_lib/cyclone10lp_atoms.v

    # Path name 'D:/build/swbuild/SJ/nightly/18.1std/625/l64/work/modelsim/eda/sim_lib/cyclone10lp_atoms.v' doesn't exist.