Modelsim instance window error

Hello,

I have a problem with ModelSim Altera Starter Edition 10.1d (used with Quartus II 13.1). The project is based on Cyclone III, so I cannot use newer software. The problem started, when I moved the project to the newer computer with Win10. Reinstalation did not help.

I'm receiving following errors when trying to import design via tcl sript:

# **** Error: LoadCompleteQ cmd: Transcript::ViewSimPanes sim
# ****        ** Error: (vsim-4005) Invalid argument 'AssertionScope'.

# ContextView configure: -filter <filter-list>** Error: (vsim-4005) Invalid argument 'UPF'.

# ContextView configure: -filter <filter-list>
# ** Error: (vsim-4005) Invalid argument 'AssertionScope'.

# ContextView configure: -filter <filter-list>** Error: (vsim-4005) Invalid argument 'UPF'.

# ContextView configure: -filter <filter-list>
#     while executing
# "Structure::CreateWindow $dataset_name"
#     (procedure "Transcript::ViewSimPanes" line 26)
#     invoked from within
# "Transcript::ViewSimPanes sim"
#     ("eval" body line 1)
#     invoked from within
# "eval $p $tankNamespace "

And

# **** Error: LoadCompleteQ cmd: Transcript::ViewSimPanes sim
# ****        can't rename to "::.main_pane.structure.interior.cs.body.struct": command already exists
# can't rename to "::.main_pane.structure.interior.cs.body.struct": command already exists
#     while executing
# "$vsimPriv(windowmgr) ShowWindow $windowobj"
#     (procedure "Structure::CreateWindow" line 23)
#     invoked from within
# "Structure::CreateWindow $dataset_name"
#     (procedure "Transcript::ViewSimPanes" line 26)
#     invoked from within
# "Transcript::ViewSimPanes sim"
#     ("eval" body line 1)
#     invoked from within
# "eval $p $tankNamespace "

The simulation is running, but I cannot see a project structure window.

I created a test project to investigate that. The whole code in project is:

Main file:

module Test_Project(
	A,
	B,
	AND_OUT
);

input wire	A;
input wire	B;
output wire	AND_OUT;

assign	AND_OUT = A & B;

endmodule

Test bench:

`timescale 1 ns / 1 ns
module TestBench();
	reg A=1'b0; 
	reg B=1'b1;
	wire	AND_OUT;

	
	Test_Project uut(
		A,
		B,
		AND_OUT
	);
	
	always #20 A = ~A;
	always #40 B = ~B;
	
endmodule

TCL file, that loads the script:

#init_tk
echo "Creating library"

cd {D:\Projects\FPGA\Test_Project\simulation\modelsim}

vlib ./work
vmap work ./work

#echo "Adding library"
#vlib altera_mf_ver
#vmap altera_mf_ver ./altera_mf_ver

#echo "Compiling library"
#vlog -work ./altera_mf_ver "D:/Software/altera/13.1/quartus/eda/sim_lib/altera_mf.v"

echo "Compiling modules"
vlog -work ./work "D:/Projects/FPGA/Test_Project/Test_Project.v"
vlog -work ./work "D:/Projects/FPGA/Test_Project/TestBench.v"


echo "Load/Simulate the design"
vsim -L altera_mf_ver TestBench -t ns

echo "Done."
vsim -L altera_mf_ver TestBench -t ns

echo "Done."

Do you know where the problem could be?