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Altera_Forum
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12 years ago

ModelSim incorrectly simulates FPGA design

My AHDL program runs as expected on my FPGA, but when I simulate it in ModelSim, the result is wacky. Tools/Equipment: Windows 7 Quartus II 32-bit v12.0 sp2 Web Edition ModelSim SE-64 10.0c,...
Altera_Forum's avatar
Altera_Forum
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12 years ago

you might get a warning from quartus, finding where it is may be difficult. If all the code was synchronous, you wouldnt get such a loop. But you only posted a small code snipppet.

Of course having AHDL is going to make debugging a whole lot harder.

But if its working on FPGA, why the worry? (of course, again, being AHDL, its going to make changes a whole lot harder, as above.)