Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

ModelSim incorrectly simulates FPGA design

My AHDL program runs as expected on my FPGA, but when I simulate it in ModelSim, the result is wacky. Tools/Equipment: Windows 7 Quartus II 32-bit v12.0 sp2 Web Edition ModelSim SE-64 10.0c,...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

reaching the iteration limit usually means you have a logic loop. There is nothing wrong with modelsim. The problem is with your design.