ModelSim Incorrect PLL output frequency

Did you already measure the period of the Pll input clock?

it looks like your input clock is 1/6 of the period.

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# Note : Cyclone IV E PLL locked to incoming clock

# Time: 312 Instance: sidewinder2_red_fpga_tb.sidewinder2_red_fpga_top_i nst.pll_clk_25_inst.altpll_component.cycloneiii_pl l.pll3

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That's ok, I think. I have also a design, where Modelsim gives me the same comment for a Cyclone IV (... /TopFpga_inst/IClockManager_inst/altpll_component/cycloneiii_altpll/m5).