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Altera_Forum
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15 years ago

Modelsim: High Z in Gate Level Simulation

In my gate level simulation, some of the signals are in High Z state from beginning to end of simulation. It is not happening in RTL level simulation. May i know what are the possible reason can ca...
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Altera_Forum
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15 years ago

Pletz is right. High 'Z' is the simulators way to tell, that the respective bits have been removed in synthesis, because no FPGA output depends on it.