Modelsim: High Z in Gate Level Simulation

I don't use any tristate in the design. I found out that the Z is caused by unused bits in internal signals(vector). I have no idea why does modelsim display unused bits in high Z condition.

eg.

reg [3:0] a ;

reg [3:0] b;

reg [7:0] result;

output reg [3:0] result_truncate;

result <= a * b;

result_truncate <= result[7:4];

the signal result[3:0] will be high Z.

How to set the modelsim to display the Z value as zero value?

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Unitialized signals would show as 'U', driver conflicts as 'X'.

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from my past experience in using the modelsim, whenever deal with X, it always relate to uninitialized of signal if the X happen in the beginning of the simulation. It uses X instead of U. Besides, X also represents driver conflict when in the middle of simulation.