Altera_ForumHonored Contributor16 years agoModelsim: High Z in Gate Level Simulation In my gate level simulation, some of the signals are in High Z state from beginning to end of simulation. It is not happening in RTL level simulation. May i know what are the possible reason can ca...Show More
Recent DiscussionsConnection bit order between hierarchyFree Licence for Max+PlusIIMAX10 ADC - getting it to simulate in ModelsimFailed to run ip-setup-simulation:Compile option not saved (reversed to default)