ModelSim Gate-level Simulation with SystemVerilog

With QII 9.0 SP1, I am having trouble running an SV test bench in a gate-level simulation. I have setup the test bench for compilation in nativelink per the docs. If I choose RTL simulation, then the TB compiles and works. If I choose to do a gate-level sim, then ModelSim gives me an error on every SV keyword.:confused:

I have the TB extension set to .sv which the MS docs say is all that is necessary. Also inspecting the .do file shows the -sv qualifier in the RTL sim, but not in the gate-level sim.

I tried to copy the .do file with the -sv added and set it as the script for TB compilation. It didn't work. Does anybody know how to setup a gate-level simulation for nativelink in QII that uses an SV test bench? I REALLY do not want to switch to the command-line interface.