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Altera_Forum
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16 years ago

ModelSim fails to recognise internal component connections

I am trying to simulate in Modelsim (altera or xilinx web edition) a verilog only project consisting of top level and few components. All components have wire type outputs. The problem is that Mod...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Thanks pletz,

it works now. It was due to my initial values at declaration. I was vhdl minded apparently.

Many thanks for your time