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Altera_Forum's avatar
Altera_Forum
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11 years ago

MODELSIM error vsim-3807

Hi folks,

I have recently encountered a problem which I have not seen before, even though I am following the same design/synth/sim flow as I usually do. Basically, when I go to RTL simulate in MODELSIM i get the VSIM-3807 error, on closer inspection it says I have type mismatch in one of my VHDL files.

The VHDL file i have created has the following declarations:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

and I only use UNSIGNED and no STD_LOGIC_VECTORS although i do use STD_LOGIC.

I have various megafunctions as well as a BSF file created from my own vhdl file all connected in a BDF. i then create a vhdl file from this BDF and include in the project and set as top level entity (the BDF file is not included in the project). And then I compile.

When I examine the created vhd file against the errors shown in MODELSIM, i can see that the component port declarations used are STD_LOGIC_VECTOR even though in my original VHDL file they were defined as UNSIGNED.

The declarations at the top of the vhd file created from my BDF does not include the IEEE.NUMERIC_STD.ALL;

I don't understand why this type mismatch has occurred.

Can anyone give me some hints please

Many thanks in advance

deBoogle

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    when you convert from BSF to vhd it will make everything a std_logic/std_logic_vector, so any connections you will have to ensure there is an appropriate type conversion.

    Its one of the reasons why using the Quartus graphical editor is generally a bit rubbish.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    So we meet again Sir,

    i quite agree that the graphical editor is less than ideal. What I dont understand is that I have never come across this before? I have been using this design method for 2 years or so and this is the first time it has raised its ugly head. I wondered if there is some way to tell quartus to use a specific library and type when it converts the BDF to a vhd. But I couldnt find any info out there to do this...

    thanks for your help.

    deBoogle
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Theres two ways of converting:

    vhd -> bdf - accepts integers, std_logic_vectors and integer on ports (I think)

    bdf -> vhd - will assume everything is a std_logic_vector (or if you have a 2d array, it will use the custon std_logic_2d_array_t, so best avoided)

    There is no way to tell quartus to use any specific libraries. If you want to do anything other than the above, I suggest writing the code in VHDL (which is much better for version control and tool migration anyway!)