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Hi all,
When I try to simulate the example of link_port downloaded from altera website, the error in the title appears.
The following is the error message copied from the transcript windows of Modelsim:# Loading E:/508/fpga/sim/altera_mf.dffep# ** Fatal: (vsim-3367) E:/508/fpga/sim/altddio_out.v(84): UDP ports cannot be connected by name.# Time: 0 ns Iteration: 0 Instance: /data_order/lt0/lp_tx_data_3/genblk1 File: E:/508/fpga/sim/altddio_out.v# FATAL ERROR while loading design# Error loading design
According to the error message, I have examined the port connections. The component "altera_mf.dffep" is instantiated with correct names in the file "altddio_out.v". So i can't fix this problem:(. what can i do next?
The two files: "altera_mf.dffep" and "altddio_out.v" are required when the files "lp_rx.v" and "lp_tx.v" are compiled.
Thanks a lot!
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I have encounted the same problem, have you solved this problem?
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