Forum Discussion
Honored Contributormodelsim error 211
We have various versions of Quartus and modelsim (all the free web versions, including 15.1 downloaded yesterday) installed on several PCs and modelsim was working until recently, however on all PCs, versions and designs it now gives error 211 and closes after a few seconds. There is nothing in the modelsim transcript file about the error. I have searched the forum and googled and the only thing I can find are references to license issues, however this is all with the free version. Here is the last entry in the transcript file:# vcom -2008 -work work {C:/projects/FPGAs/GEP/system keith 15Oct15/228-603-01-issB/Design Files/AXES/tbMOVING_AVERAGE_FOR_ADS8332.vhd}# Model Technology ModelSim ALTERA vcom 10.3c Compiler 2014.09 Sep 20 2014# Start time: 10:00:24 on Dec 01,2015# vcom -reportprogress 300 -2008 -work work C:/projects/FPGAs/GEP/system keith 15Oct15/228-603-01-issB/Design Files/AXES/tbMOVING_AVERAGE_FOR_ADS8332.vhd # -- Loading package STANDARD# -- Loading package TEXTIO# -- Loading package std_logic_1164# -- Loading package MATH_REAL# -- Loading package NUMERIC_STD# -- Loading package AVERAGE_PACKAGE# -- Compiling entity tbMOVING_AVERAGE_FOR_ADS8332# -- Compiling architecture tbMOVING_AVERAGE_FOR_ADS8332_arch of tbMOVING_AVERAGE_FOR_ADS8332# End time: 10:00:25 on Dec 01,2015, Elapsed time: 0:00:01# Errors: 0, Warnings: 0# # vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cycloneive -L rtl_work -L work -voptargs="+acc" tbMOVING_AVERAGE_FOR_ADS8332# vsim "+altera" -l msim_transcript -do "228-603-01-issB_run_msim_rtl_vhdl.do" # Start time: 10:00:26 on Dec 01,2015# Loading std.standard# Loading std.textio(body)# Loading ieee.std_logic_1164(body)# Loading ieee.math_real(body)# Loading ieee.numeric_std(body)# Loading work.average_package(body)# Loading work.tbmoving_average_for_ads8332(tbmoving_average_for_ads8332_arch)# Loading work.moving_average_for_ads8332(behaviour)# Loading work.moving_averager(rtl)
22 Replies
Altera_ForumThe Modelsim Reference Manual Lists all of the exit codes
--- Quote Start --- 211 Segmentation violation (SIGSEGV) --- Quote End --- Basically, Modelsim has crashed. It is probably something in your code causing the crash (when it shouldnt). I see you are compiling with the -2008 vhdl switch. Any chance you can post all the code here so we can try? Otherwise you'll need to raise a ticket with Mentor (and you wont see an update until altera issue a new version).- Altera_Forum--- Quote Start --- The Modelsim Reference Manual Lists all of the exit codes Basically, Modelsim has crashed. It is probably something in your code causing the crash (when it shouldnt). I see you are compiling with the -2008 vhdl switch. Any chance you can post all the code here so we can try? Otherwise you'll need to raise a ticket with Mentor (and you wont see an update until altera issue a new version). --- Quote End --- Tricky thanks for the quick reply but I have tested files which I know worked before. I have zipped an example project to a zip folder but the attachments function will not let me load it.
- Altera_Forum
I think you need a certain number of posts before you can post attachments. Try putting it on google drive or dropbox or similar.
- Altera_Forum--- Quote Start --- I think you need a certain number of posts before you can post attachments. Try putting it on google drive or dropbox or similar. --- Quote End --- Project is in the attached dropbox link, so I can attach txt not a zipped folder but can't paste! tb_IOTEST is a test bench for block IOTEST. Thanks.
- Altera_Forum
tb_IOTEST ran just fine for me.
Some notes: 1. GPIO_0 and GPIO_1 bits 7:4 never get assigned a value. 2. You are using both edges of the clock, which is illegal inside an FPGA. - Altera_Forum
Yes it used to run fine for me. I know it is not good code but it was a very small design so easy to send. So why are all our copies of Modelsim crashing? Are there any tests I can do?
- Altera_Forum
How are you loading the code? it is using tcl scripts, a modelsim project or via native link?
- Altera_Forum
Tried starting Modelsim from Quartus automatically at the end of compile, from Quartus tools>run simulation tool and also running Modelsim with a tcl script.
- Altera_Forum
what is in the tcl script? I manual compiled just iotest.vhdl and tb_iotest.vhd and there were no problems. Are there extra files in the tcl script that shouldnt be there? Are there non-hdl files in the script? have you got some files renamed to have a .vhdl extension that shouldnt?
I notice there are bdf files - are you trying to simulate these? have you converted them to HDL first? - Altera_Forum
You can see from the transcript file in my 1st post which is for a different design but is up to the point where it crashed when run from Quartus. We are not trying to simulate bdfs. The whole project folder was in the zip, there are only 3 vhdl files inc the test bench.
When you say you manually compiled how did you do this?
