modelsim does not generate clock signal

Thank you for all replies!

Well. Firtsly I created Testbench skeleton by Processing -> Start -> Test bench Writer

Then i added its link in Assingments -> Settings -> Simulation -> Native link settings

I modified TB with a few lines for modelsim to generate clock signal (just to try how it works)

But it is not work, even if i try to assing anything to 1'b1 or whatever.

Please guide how it supposed to work :c

clk_clk generated as reg