modelsim does not generate clock signal

Hi,

--- Quote Start ---

initial begin

clk_clk = 0;

end

always# 10 clk_clk = ~clk_clk

--- Quote End ---

Let me know,

1. Are you able to compile Design & Testbench successfully?

2. All Inputs/Outputs are declared & initialized properly or not(declaration of clk_clk should be reg)?

3. can you provide code?

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards

Vikas Jathar

(This message was posted on behalf of Intel Corporation)