modelsim clock network stuck StX (gate level sim)

Well, I did target the Cyclone V series as this is the Lite version of Quartus II 17.1 (Windows) that I'm using, ModelSim is the Intel starter version.

I did modify the testbench a little, nothing major.

// Test bench for shiftRegister.sv
//
// test_vector.txt (bb_b_b <in>_<en>)
timeunit 1ns/100ps;
module shiftRegister_tb;
    // Glue for the instance
    logic            in;
    logic        clk;
    logic        en;
    logic         d_out;
    // Internal, needed by testbench
    integer        tst_vec;
    integer        scan_file;
    logic             t;
    
    always# 1 clk = ~clk;
    
    initial begin
        tst_vec = $fopen("test_vector.txt","r");
        // just be clean and set an initial value.
        clk = 1;
        en = 0;
        in = '0;
        t = '0;
    end
    always @(posedge clk) begin
        // Start looping the test vector to generate our input
        if(!$feof(tst_vec)) begin
            scan_file = $fscanf(tst_vec,"%b",t);
            in = t;
            en = t;
        end
        else // when done just go quiet...
        begin
            en = 0;
            in = '0;
            $finish;
            $fclose(tst_vec);
        end
    end
    
    shiftReg dut (
        .in(in),
        .clk(clk),
        .en(en),
        .d_out(d_out)
    );
endmodule

I had to change the name of the DUT as I didn't want it to overwrite the RTL simulation database. I've uploaded the netlist also. Have a look at it. The shiftReg.v file is the gate netlist. The other two are the design and TB files.