Modelsim ASE issue.

Ive faced difficulty simulating verilog hdl code in ModelSim:

** Error: (vsim-3033) D:/Work/Workspace/Opt_ch/FPGA_conf/fifo.v(74): Instantiation of 'dcfifo' failed. The design unit was not found.

I've tried using script http://www.altera.com/support/examples/tcl/tcl-modelsim.html?gsa_pos=1&wt.oss_r=1&wt.oss=tcl%20modelsim but it did not help. What am I doing wrong?