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I can't read vhdl/verilog source because of too small font around 1pt.
tools->edit preference->source windows->fixed font or text font size setting change was no effect.
This problem is same after version down to quartus prime 15.1.
Modelsim(vsim) looks porting soft from windows .net.wm application. So I can't find how to change X11 font setting.
Does anyone know the workaround of this problem ?
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I second that question. Modelsim 10.4d, solved the freetype2 problem, compiled and symlinked the 32-bit libraries (freetype2-2.5.0.1-1-i686). Modelsim starts with no warnings but the source window font is not readable (very small).
I can't find a solution online, would someone at Altera point us in the right direction?
Honored Contributor
