Transcript is :-
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity ddr_uniphy_hc_example_sim_e0_if0_id_router
# -- Compiling architecture RTL of ddr_uniphy_hc_example_sim_e0_if0_id_router
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity ddr_uniphy_hc_example_sim_e0_if0_addr_router
# -- Compiling architecture RTL of ddr_uniphy_hc_example_sim_e0_if0_addr_router
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
# ** Error: (vcom-7) Failed to open design unit file "./..//submodules/ddr_uniphy_hc_example_sim_e0_if0_c0_csr_translator_avalon_universal_slave_0_agent_rdata_fifo.vho" in read mode.
#
# No such file or directory. (errno = ENOENT)
# ** Error: C:/altera/13.0/modelsim_ase/win32aloem/vcom failed.
# Error in macro ./
run.do line 11
# C:/altera/13.0/modelsim_ase/win32aloem/vcom failed.
# while executing
# "vcom "$QSYS_SIMDIR/submodules/ddr_uniphy_hc_example_sim_e0_if0_c0_csr_translator_avalon_universal_slave_0_agent_rdata_fifo.vho" "
# ("eval" body line 42)
# invoked from within
# "com"
# invoked from within
# "if {[file exists msim_setup.tcl]} {
# source msim_setup.tcl
# dev_com
# com
# # the "elab_debug" macro avoids optimizations which preserves signals so tha..."