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Altera_Forum
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9 years ago

modelsim-Altera "create wave" problem with generic

I am using Quartus Prime Lite 15.1/modelsim-Altera starter 10.4 - university edition (professor) When I create fixed ports in VHDL ... port (aa, bb: in STD_LOGIC_VECT...
Altera_Forum's avatar
Altera_Forum
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9 years ago

Without elaborating the design, modelsim has no way of knowing how wide the busses are.