Forum Discussion
Altera_Forum
Honored Contributor
17 years agoAs vjAlter states, Altera PLLs are generally correctly simulated also by ModelSim functional simulation. This is an important feature, cause gate-level simulation, besides it's slow operation, hasn't much worth in code debugging. It's mainly useful to check the timing of a design.
I think, it may be a problem of specifying the required libraries for the simulation. Cause I'm mostly using VHDL, where the library references are part of the code, I don't have to care for this issue. As another point, when simulating PLLs, the simulator resolution must be always set to 1 ps.