ModelSim Altera and megafunction

You shouldn't need to use gate level simulation.

I assume you mean altpll megafunction, I can't see any megafunction named clock_pll. Possibly clock_pll is the name of your variation file, and you used VHDL when creating the megafunction variation.

When you invoke the MegaWizard, you can select the HDL language for your variation. Make sure you are selecting Verilog.

But note that most designs don't require a full PLL simulation model for RTL level simulation. I usually add a small dummy PLL module to the testbench.